FIG. 1 is a circuit diagram of a portion of a conventional memory device 100. The memory device 100 includes a plurality of memory cells M, M′, which are respectively and controllably coupled to a plurality of bit lines BL, BL#. The memory cells M and M′ are also coupled to a word line WL. Typically, a memory device 100 would have a large number of memory cells, and therefore a large number of bit lines and word lines, however, for simplicity, FIG. 1 only illustrates two memory cells M, M′, two bit lines BL, BL#, and a single word line. Each memory cell M, M′, might be, for example, a dynamic random access memory (DRAM) cell, such as a conventional one transistor one capacitor (1T1C) DRAM cell. In a memory device 100, each bit line BL is associated with another bit line such as bit line BL#. Each pair of associated bit lines BL, BL# is coupled to equalization circuitry 110 and sense amplifier 120. As illustrated, the equalization circuitry 110 comprises transistors Q1, Q2, and Q3 and the sense amplifier 120 comprises transistors Q4, Q5, Q6, and Q7.
The memory device 100 also includes transistors Q8, Q9, Q10, and Q11 and nodes A, B, C, D, E, F, G, N, and P, which are used to control the operation of the equalization circuitry 110 and the sense amplifier 120. The memory device 100 also includes additional control circuitry, which is not illustrated in order to avoid cluttering the figure. Nodes A, D, F, and G, are preferably coupled to a source of a predetermined voltage (e.g., dvc2), while nodes E, B, and C are coupled to control signals as described below. As used in the application, the dvc2 voltage refers to a voltage level at half the level of the D.C. supply voltage.
The sense amplifier 120 is comprised of a positive portion 121 and a negative portion 122. Each portion 121, 122 includes a common node. In the positive portion 121 the common node is node P, while in the negative portion 122 the common node is node N. Control signals are supplied to the common nodes P, N as described below to operate the portions 121, 122 of the sense amplifier 120.
Now also referring to the timing diagram of FIG. 3, a read operation of memory cell M is explained. The timing diagram of FIG. 3 is divided into ten equal length time periods T1–T10. Each time period may correspond, for example, to a clock cycle in a synchronous DRAM (SDRAM) device, or a half clock cycle in a double data rate SDRAM device.
At time period T1, the word line is set to a low state, bit line BL has been set to a high state and associated bit line BL# has been set to a low state (not shown). Control signal LNSA, which is supplied from node C, is set to a low state, causing transistor Q11 to be non conducting. Control signal LPSA#, which is supplied from node B, is set to a high state, causing transistor Q9 to be non conducting. Additionally, control signal EQ, which is supplied from node E, transitions from low to high.
As a result, by time period T2, transistors Q1, Q2, Q3, Q8, and Q10 begin to conduct. Transistors Q1, Q2, and Q3 operate to equalize the voltage on bit line BL associated with memory cell M and its associated bit line BL# to a same predetermined voltage, such as dvc2. Transistor Q8 conducts and sets the voltage at node P to the same voltage as node D, which as previously described is dvc2. Transistor Q10 conducts, thereby setting node N to have the same voltage as node G (i.e., dvc2).
At time period T3, control signal EQ transitions low, causing transistors Q1, Q2, Q3, Q8, and Q10 to become non conducting, and thereby causing bit lines BL, BL# and nodes P, N to float at a voltage of dvc2. This step of equalizing the voltages on bit lines BL, BL# and nodes P, N is known as an equilibrate step. As described above, the bit lines BL, BL# and nodes P, N are equilibrated to a common voltage at a common time.
At time period T4, the world line WL associated with the memory cell M is set to a high level (e.g., Vpp). The memory cell M is then coupled to its bit line BL, thereby causing the memory cell M to share its charge with the bit line BL. As a result, the voltage of bit line BL is altered. The polarity of the alternation in the voltage of bit line BL is dependent on the charge stored in the memory cell M. Bit line BL will therefore either have a higher or a lower voltage than its associated bit line BL#.
At time period T5, control signal LNSA, which is supplied from node C, transitions from low to high, and control signal LPSA#, which is supplied from node B transitions from high to low. Controls signals LNSA and LPSA# are control signals for determining when the negative 122 and positive 121 portions of the sense amplifier 120 are activated. More specifically, when control signal LNSA is high, the negative portion 122 of the sense amplifier 120, comprising transistors Q6 and Q7, is activated, and pulls the bit line having the lower voltage in the bit line pair BL, BL# to ground. When control signal LPSA# is low, the positive portion 121 of the sense amplifier 120, comprising transistors Q4, Q5, is activated and pulls the bit line having the higher potential in the bit line pair BL, BL# to a high potential. The pulling of voltages on bit lines BL, BL# occurs during time periods T5, T6, T7, and T8 and is completed by the end of time period T8.
Thus, by time period T9, the bit line of the bit line pair BL, BL# having higher potential is pulled high while the bit line of the bit line pair BL, BL# having lower potential is pulled to ground (i.e., low). In time period T9, the word line WL is also reset to its low logical state. In time period T10, control signals LNSA and LPSA# return to their original states.
It is advantageous to equilibrate a bit line pair BL, BL# to a voltage level less than dvc2. Conventionally, a lower equilibrate voltage can be achieved by bleeding voltage off the bit line pair BL, BL# after equilibrating the bit lines to dvc2. However, this method requires significant current handling within the memory device and is difficult to perform for high speed memory devices. Accordingly, there is a need and desire for a memory device and associated method for equilibrating a bit line pair to a reduced voltage than the level typically used.